Readout ASICs for the DEPFET detectors

Photograph of the DCDBv2 chip.
The schematics of the current-mode ADC, based on the current memory cells.
3D layout of the analog channel in DCDBv2 generated with the Gds2Pov software.
Automatic test of all DCDBv2 ADCs at 100MHz sampling rate.


DCD (DCD1,2,DCDBv1,v2,TCDCD1,2...) is a family of the multi-channel ADC chips for the readout of DEPFET detectors. The latest DCD version, implemented in UMC 180nm technology and optimized for Belle II pixel detector, contains 256 channels, each with a trans-impedance amplifier and two current-mode cyclic ADCs. The ADC resolution is 8-bit and the conversion time down to 160 ns. The power consumption of the ADC analog core is around 1mW and the layout area only 40 x 55 micrometers. The ADC is based on the novel current memory cells. There are 512 ADCs on the chip, all operating at the same time. The analog parts of the chip are laid-out using radiation tolerant techniques e.g. the enclosed NMOS gates. One DCD generates a continuous data stream of 2.56 GBytes/s.


The development of the current-mode ADCs for DEPFET and other detectors (a similar ADC is used in the readout-chip SPADIC for the CBM experiment) required at least six chip iterations. The latest DCD version (DCDBv2) operates at the required sampling rate (256 inputs - each 10Msaples/s) with an input-referred noise of about 70nA and 8-bits ADC resolution. The power consumption of the chip is about 1.2 W. The DCDBv2 is used for the characterization of DEPFET prototype matrices. Only minor changes will be needed for the production chip version.

The SWITCHER-family.
The output driver of SWITCHER3 chip capable to generate 10.5V pulses. The use of transistor-stacks assures that no singe transistor experiences a higher voltage than 3.5V.
The output driver of SWITCHERB chip. Radiation-tolerant high-voltage transistors Tp and Tn generate output pulses of up to 50V. The remaining devices control the gate voltages of these transistors.
SWITCHER3 test: Nanosecond-fast high-voltage output pulses.


The task of Switcher chips is switching of the DEPFET matrix and clearing of the signals by means of fast high-voltage pulses. We have designed so far six SWITCHER versions in three different high-voltage CMOS technologies.


SWITCHER2 was implemented in AMS 0.8 micrometer HV-process, it used the high-voltage transistors with thick oxide in its output drivers. This chip was used for the DEPFET development, but was not radiation tolerant enough, since the thick-oxide transistors are sensitive to the total dose effects.


SWITCHER3 was the first radiation-tolerant version. It was implemented in AMS 350nm HV-process. The output drivers were based on the stacked low-voltage transistors placed in the in deep wells. The chip generates output voltages of up to 10.5V. The use of transistor-stacks assures that no singe transistor experiences a higher voltage than 3.5V, the maximal allowed value for the thin-oxide devices.


SWITCHERS is the radiation-tolerant chip for the x-ray imager MIXS on the board of the spacecraft BepiColombo. The goal of the mission is to investigate the surface of the planet Mercury. SWITCHERS uses special radiation tolerant high-voltage transistors. These transistors generate output pulses of 50V amplitude. The chip is implemented in 350 AMS HV-process.


SWITCHERB is the first SWITCHER designed for Belle II pixel detector. The chip uses similar high-voltage drivers like SWITCHERS.


SWITCHERB18 is the version of the Belle II-type SWITCHER implemented in 180nm AMS HV-process. Thanks to the newer process, we expect a higher radiation tolerance and a lower power consumption.


All the chips have been carefully characterized and used for the readout of DEPFET detectors. The switching time for capacitive load of typically 50pF is about 5ns. Radiation tolerance of at least 30MRad has been demonstrated for SWITCHER3, -S and -B.

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