Pixel detectors in SOI technology

Photograph of the SUSOKI1 chip.
SUSOKI1: The pixel-schematics and its cross-section.
The dynamic range for a measurement time of 1 microsecond is 10000.


SUSOKI1 and 2 are the monolithic pixel detectors implemented in 200nm SOI detector technology. This is a non-standard technology developed among others by the research institute KEK and the chip-foundry Lapis-Semiconductor (formerly OKI). SOI-detector technology allows the implementation of CMOS electronics on the high-quality and high-ohmic SOI substrate (for instance a 500 micrometer thick floating-zone 7 kOhm cm substrate). The sensor diodes are implemented in the bulk underneath the buried oxide. The connections through the buried oxide are made to connect the readout electronics with the sensor diodes.

The chips contain an 8 x 8 pixel matrix with pixels of 113 x 113 micrometers size. Every pixel contains a fast and high-dynamic-range integrator. The circuit is based on an analog integrator, a comparator and a charge pump. Every time the output of the integrator exceeds a threshold, a time stamp is stored and a counter incremented by one. The use of such a two-fold measurement - the charge-to-time and the charge-to-frequency conversion - assures a high and a linear dynamic range. The dynamic range can be achieved within a relatively short measurement time of less than one microsecond.

Our SOI detector could be used for the x-ray imaging at the synchrotron-sources and the x-ray free-electron lasers (such as the European XFEL). The SOI detector is a simple and a low-cost alternative to the hybrid pixel detectors that are widely used in the mentioned applications.


We have tested the detector by using of the test pulses and the radioactive sources. The measured dynamic range for a measurement time of 1 microsecond is 10000.

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