The SPADIC Project Website

And another snapshot of the SPADIC history ...

August 2012: The second SPADIC 1.0 front-end PCB. The die is directly wire-bonded to a carrier board. The carrier board is plugged onto a small main board, which can be connected in various ways (e.g. via CBMnet over HDMI or directly to the Susibo, as shown in the picture). The main board provides various voltage regulators and other peripheral parts.

Welcome to the official SPADIC project website. On the following pages you will find very different kinds of information about the SPADIC project in general and on the SPADIC ASIC in particular.

What is SPADIC?

The SPADIC project relates to the name of the SPADIC readout chip (Self-triggered Pulse Amplification and Digitization asIC) which is intended to read out and process small electrical detector signals on a single piece of silicon. The latest SPADIC version 1.0, which is actually the 6th but first full-blown prototype, is a 32-channel mixed-signal readout chip dedicated for the readout of the transition radiation sub-detector (TRD) that will be part of the future CBM heavy-ion experiment at GSI/FAIR. SPADIC 1.0 provides low-noise and low-power analog pre-amplification, 8 bit digitization, IIR signal processing, self-triggered hit detection, neighbor readout, full pulse recording, meta data generation, synchronization mechanisms, and various other features.