SPADIC 1.0
Documentation
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SPADIC 1.0 Specification, latest Version, PDF
Latest version of the SPADIC v1.0 specification, always under construction! -
Register File Documentation (html version)
Generated documentation of the register file.
Pictures
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SPADIC 1.0 toplevel, layout
JPG, 800kByte -
SPADIC 1.0 toplevel, layout
PNG, 19MByte
Selected Milestones
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First measurement of analog test-pulses read out via test data ouput
Animated GIF, 380kByte
Setups
Setup 002: SPADIC v1.0, Front-End PCB rev. A
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PCB rev. A Bestückungsplan
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Main board schematics and layout (08/2012)
Altium project files -
Carrier board schematics and layout (08/2012)
Altium project files -
Susibo firmware for CBMnet readout (07/2013)
200 MHz, Susibo connector — Latest update on 2013-07-15.
FPGA configuration .bit .xsvf
PROM configuration .mcs .xsvf -
Basic SPADIC configuration file (09/2013)
Turns on one channel with reasonable bias settings: base_setup3.spc
Setup 001: SPADIC v1.0, 1st Front-End PCB, Susibo 2.x
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PCB Schematics (03/2012)
PDF, PCB schematics and layout -
Complete PCB Project (03/2012)
Altium PCB project files -
Hitclient (04/2012)
C++ source code -
Data stream analyzer (04/2012)
Alternative Python version -
Example data streams (04/2012)
For testing analysis software